Voltage pump with diode for pre-charge

ABSTRACT

A charge pump system for providing a voltage to a semiconductor device is disclosed. Current charge pumps use a separate pre-charge capacitor and pre-charge circuitry for the boot circuit which provides the gate voltage for the output transistor. The present invention eliminates the need for the separate pre-charge capacitor and pre-charge circuitry by the use of a single diode. The net effect is a more efficient and smaller charge pump circuit.

BACKGROUND OF THE INVENTION

[0001] I. Field of the Invention

[0002] The present invention relates to semiconductor circuits and tocharge pumps used therein. More specifically, the invention relates to asimplified charge pump system for providing a voltage to varioussemiconductor integrated circuits or portions thereof The invention isparticularly applicable to dynamic random access memory devices (DRAMs).

[0003] II. Description of the Related Art

[0004] System designs are routinely constrained by a limited number ofreadily available power supply voltages (Vcc). For example, consider aportable computer system powered by a conventional battery having alimited power supply voltage. For proper operation, different componentsof the system, such as display, processor, and memory components employdiverse technologies which require power to be supplied at variousoperating voltages. Components often require operating voltages of agreater magnitude than the power supply voltage and, in other cases, avoltage of reverse polarity. The design of a system, therefore, mustinclude power conversion circuitry to efficiently develop the requiredoperating voltages.

[0005] One such power conversion circuit is known as a charge pump. Thedemand for highly-efficient and reliable charge pump circuits hasincreased with the increasing number of applications utilizing batterypowered systems, such as notebook computers, portable telephones,security devices, battery-backed data storage devices, remote controls,instrumentation, and patient monitors, to name a few.

[0006] Inefficiencies in conventional charge pumps have led to reducedsystem capability and lower system performance in both battery andnon-battery operated systems. Inefficiency can adversely affect systemcapabilities, e.g., limited battery life, excess heat generation, andhigh operating costs. Examples of lower system performance include lowspeed operation, excessive operating delays, loss of data, limitedcommunication range, and inability to operate over wide variations inambient conditions including ambient light level and temperature.

[0007] In addition to constraints on the number of power supply voltagesavailable for system design, there is an increasing demand for reducingmagnitudes of the power supply voltages. The demand in diverseapplication areas could be met with highly efficient charge pumps thatoperate from a supply voltage of less than five volts.

[0008] Such applications include memory systems backed by 3 volt standbysupplies, processor and other integrated circuits that require eitherreverse polarity substrate biasing or booted voltages outside the rangeof 0-3 volts for improved operation.

[0009] One such known charge pump system is a two stage charge pump. Twostage charge pump systems have proven to be effective at providingsemiconductor components with the necessary input voltage particularlywhere the system voltage is below 3 volts.

[0010] For purpose of simplification, the following discussion willfocus on the charge pumps which must produce a positive voltage greaterthan the most positive supply voltage Vcc; however, the conceptsdiscussed are also applicable to charge pumps designed to produce anegative voltage from a positive Vcc voltage.

[0011] Most charge pumps comprise some variation of the basic chargepump 10 shown in the schematic diagram of FIG. 1. The basic charge pump10 configuration includes a ring oscillator 12 which provides a squarewave or pulse train having voltage swings typically between ground andthe most positive external power supply voltage, Vcc. An inverter 14,buffer amplifier, or Schmnitt trigger circuit may be used to sharpen theedges of the oscillating output signal of the ring oscillator 12. Whenthe ring oscillator 12 produces a voltage close to ground, the input toa capacitor 16 from inverter 14 is low. When the input to capacitor 16is low, node 22 passes a charge of Vcc through diode 18 to node 26. Atnode 26 the received charge is approximately Vcc minus a thresholdvoltage, i.e. Vcc-Vt (where “Vt” is the threshold voltage). Since theinput to capacitor 16 is low, capacitor 16 is pre-charged to the voltageVcc-Vt at node 26.

[0012] When the ring oscillator 12 produces a voltage close to Vcc, theinput to capacitor 16 from inverter 14 is high. During this period, Vccis supplied to the capacitor 16 and, together with the pre-charged valueof Vcc-Vt, passes a charge 2Vcc-2Vt to the load voltage terminal 24,Vccp. The additional Vt voltage drop is caused by diode 20. Vccp is theoutput voltage of charge pump 10. Capacitor 16 is prevented fromdischarging to node 22 by diode 18. Given an input voltage of Vcc, Vccpwill typically result in twice the voltage of Vcc, minus the thresholdvoltages, 2Vt.

[0013] In the charge pump 10, one pulse of current is delivered to theload voltage terminal 24 for every clock cycle of the ring oscillator12, during the half of the clock cycle when the output of ringoscillator 12 is high. When the output of ring oscillator 12 is low, theother half of the clock cycle, capacitor 16 is pre-charged and voltageis not delivered to the load voltage terminal 24. These half clockcycles are commonly referred to as phases. Therefore, the charge pump 10delivers a load voltage during a first phase and pre-charges capacitor16 during a second phase. Although this second phase is necessary topre-charge the capacitor 16, since no current is delivered to the loadvoltage terminal 24 during this second phase, it may be difficult toattain and maintain a final desired voltage, Vccp. Accordingly, chargepumps 10 have typically included two FIG. 1 circuits to operate out ofphase with their outputs commonly connected to produce the load voltageat terminal 24 for each cycle of the ring oscillator 12 by utilizingboth states of each ring oscillator cycle. This is known in the art as atwo phase pump.

[0014] In most integrated electronic circuits, including memory chips,it is desirable that the final pump voltage at the load be reached asquickly as possible. Proper device functions and attributes, such as theintegrity of stored data, cannot be guaranteed until the pump voltagehas reached the proper value. However, the circuitry presently used forsuch a system is often inefficient in terms of size, power consumptionand number of components. Therefore, there exist a need for a moreefficient charge pump system.

SUMMARY OF THE INVENTION

[0015] The present invention relates to an improved charge pump system.Current charge pump systems contain a first boot circuit to provide apump voltage Vccp as an output through an output transistor. Typically,such systems also contain a second boot circuit to provide a voltagegreater than the pump voltage Vccp for driving the gate of the outputtransistor, to ensure that the pump voltage Vccp produced by the firstboot circuit is passed to the drain of the output transistor andprovided as output voltage Vccp. The present invention eliminates theneed for the separate pre-charge capacitor and associated pre-chargecircuitry found in current systems to pre-charge the capacitor of thesecond boot circuit, through the use of a single strategically placeddiode. The net effect is a more efficient and smaller charge pumpcircuit.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The foregoing and other advantages and features of the inventionwill become more apparent from the detailed description of preferredembodiments of the invention given below with reference to theaccompanying drawings in which:

[0017]FIG. 1 is an illustration of a conventional charge pump;

[0018]FIG. 2 is an illustration of a known two phase charge pump system;

[0019]FIG. 3 is a graphical representation of voltages at various nodesof FIG. 2;

[0020]FIG. 4 is an illustration of an exemplary embodiment of thepresent invention;

[0021]FIG. 5 is a graphical representation of the voltages at variousnodes of FIG. 4;

[0022]FIG. 6 illustrates a processor-based system employing the chargepump system of FIG. 4; and

[0023]FIG. 7 is an illustration of an exemplary embodiment of thepresent invention with back to back diodes.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0024] Understanding a conventional charge pump, depicted in FIG. 2, isnecessary to fully comprehend the present invention, as the presentinvention improves upon the circuit of FIG. 2. FIG. 2 illustrates a twophase charge pump system 1000 which supplies a pump voltage Vccp at anout terminal. The charge pump system 1000 includes a two phase clockgenerator 1020; two first boot circuits 1040, each of which supplies acharge pump voltage Vccp during a respective one of the two operationalphases; two second boot circuits 1060, each of which supplies a gateoperating voltage to a respective output transistor 134, 136 to gate theoutput of the first boot circuit 1040 to a Vccp output terminal, andadditional circuitry.

[0025] The two phase clock generator 1020 receives an oscillating signalfrom oscillator 1100 and produces two logical phase signals 3002, 3004therefrom. The charge pump system 1000 is designed symmetrically, suchthat, one half of the pump circuit (top half) 5000 provides a pumpvoltage during one phase of the clock cycle and the second half of thepump circuit (bottom half) 5002 provides a pump voltage during a secondphase of the clock cycle.

[0026] The two phase clock generator 1020 has an input 1080 forreceiving an oscillating signal (Vcc) produced by oscillator 1100. NANDgates 1140 and 1160, formed as a flip flop, use inverter 1120 and theoscillator input to latch and produce outputs of opposite states. Whenthe input 1080 to the two phase clock generator 1020 is high, the outputof NAND gate 1140 is also high while the output of NAND gate 1160 islow. Likewise, when the input 1080 is low, the output of NAND gate 1140is low while the output of NAND gate 1160 is high.

[0027] Taking the top portion of the circuit 5000, which provides a pumpvoltage during a first phase, as an example, clock signal 3002 of thetwo phase clock generator 1020 is connected to the first boot circuit1040 and the second boot circuit 1060. The first boot circuit 1040operates similar to charge pump system 10 of FIG. 1. The first bootcircuit 1040 receives clock signal 3002, as clock signal 3010, afterhaving passed through one or more inverters 1180, 1220-1242 and a NANDgate 1200. The inverters 1180, 1220-1242 and a NAND gate 1200 are usedfor cross coupling of the top and bottom circuit portions 5000, 5002, toensure that the rising and falling edges of clock signals 3002 and 3004from two phase clock generator 1020 are properly aligned for each phase.Signal skew between clock signals 3002 and 3004 could result in a lossof efficiency of the charge pump. Similar to charge pump system 10 ofFIG. 1, when the clock signal 3010 to capacitor 1380 is low, capacitor1380 is pre-charged with source voltage Vcc minus a threshold voltage(Vcc-Vt) from node GØ, where GØ received its initial charge from Vcc atnode VØ passed through diode 1450. After the charge pump system 1000 hasbeen operating past the initial clock cycles, transistor 1860 suppliesGØ with the pre-charge voltage, as the gate of transistor 1860 is drivento a level above Vcc+Vt when clock signal 3010 is low because the gateof transistor 1860 is cross coupled to the bottom portion of thecircuit. The boosted gate level on transistor 1860 allows GØ to beprecharged to a full Vcc level. When clock signal 3010 to capacitor 1380goes high, similar to capacitor 16 of FIG. 1, Vcc is supplied from clocksignal 3010 to capacitor 1380 and together with the pre-charged value(Vcc) passes a final charge of 2Vcc to node GØ. This function istypically referred to as booting or pumping the voltage. Capacitor 1380is prevented from discharging to Vcc by diode 1450. This final voltageof 2Vcc at node GØ is then passed to the source of output transistor134.

[0028] The second boot circuit 1060 is provided with a clock signal,which is delayed by delay element 1760. Second boot circuit 1060provides the gate voltage for output transistor 134. This gate voltagemust be higher than the voltage 2Vcc at node GØ in order to properlydrive the gate of transistor 134, such that the final voltage at node GØwill be most efficiently passed to the drain of transistor 134 whichresults in Vccp. To achieve this higher output from the second bootcircuit 1060, capacitor 1480 of the second boot circuit 1060, similar tothe charge pump system 10 of FIG. 1, is first precharged to Vcc throughtransistor 1880, then is further precharged to 2Vcc-Vt throughtransistor 1560 by capacitor 1640. The second boot circuit 1060 thenadds another Vcc voltage produced by the delayed clock signal at 3006,to this pre-charge voltage to produce a voltage of 3Vcc-1Vt at node HØfor driving the gate of transistor 134. Thus, the output of the secondboot circuit 1060 will be greater than 2Vcc in order to properly drivethe gate of output transistor 134. Since the gate voltage of 134 onlyneeds to be 1Vt above HØ, diode 1920 is advantageously used to routeexcess charge from HØ to GØ and through transistor 134 to Vccp. The Vtof diode 1920 should be at least as high as the Vt of transistor 134 (alittle higher is better).

[0029] In operation, capacitor 1480 is pre-charged through node HØ bythe pre-charge circuitry which contains pre-charge capacitor 1640;pre-charge transistors 1560 1680; and pre-charge diode 1600. With thispre-charge circuitry, node HØ is provided with an initial voltagegreater than Vcc, preferably 2Vcc-1Vt, which is produced by thepre-charge voltage of Vcc supplied from Vcc at node 1520 throughtransistor 1680 which is booted to 2Vcc when the clock signal at theinput to capacitor 1640 goes high. This voltage, now 2Vcc passes throughtransistor 1560 which has a Vt voltage drop, providing a voltage of2Vcc-1Vt as a pre-charge voltage at node HØ. In other words, a voltageof 2Vcc-1Vt is provided to precharge node HØ. Thus, when the delayedclock signal 3006 (Vcc) is presented at the input of pre-chargecapacitor 1480 a charge greater than 2Vcc results, typically 3Vcc-1Vtwhich gates on transistor 134 through node CØ which is connected to nodeHØ. NAND gate 1400 is used to provide a shorter path for the low edge ofclock signal 3002 so that clock signal 3006 goes low prior to clocksignal 3010 going low to avoid coupling Vccp to GØ after GØ falls.

[0030] The result is a final voltage at node CØ which is higher thanthen the final voltage at node GØ. Transistor 134, having a sourcevoltage of 2Vcc (GØ) and a gate voltage of 3Vcc-1Vt (CØ), passes 2Vcc toits drain as output Vccp. In practice the actual potential at Vccp maynot reach 2Vcc due to non-ideal devices, output loads, etc. Also, it maynot be desired to have a full 2Vcc level at Vccp, however passing thefull charge from node GØ to Vccp provides greater efficiency especiallyduring power up conditions when Vcc is not at its full potential.

[0031] The bottom portion 5002 of the FIG. 2 circuit is a mirror imageof the top portion of the circuit and is functionally equivalent. Thebottom portion of the circuit, however, receives clock signal 3004 whichis 180 degrees out of phase with clock signal 3002. Together bothportions of the circuit supply a continued booted voltage Vccp at theVccp output terminal.

[0032] Typically a Vccp voltage regulator is used to control theoscillator 1100 such that the oscillator 1100 is shut off when Vccp isequal to or greater than a desired value. Allowing for additionalvoltage drops and circuit losses, exemplary values for voltages referredto herein are, Vcc=3 volts, Vccp=4.6 volts, and Vt=0.7 volts. It will beunderstood that different voltage levels could also be used.

[0033]FIG. 3 illustrates various voltages at nodes depicted in FIG. 2.In particular the voltages at nodes GØ and HØ, in correlation with theclock, delayed clock, the Vccp voltage generated by one phase of thecharge pump system 1000, and the total Vccp are displayed. A close studyof FIG. 3 indicates that GØ pre-charges capacitor 1380 to Vcc, which isbooted to 2Vcc. Furthermore, HØ pre-charges capacitor 1480 to 2Vcc-1Vt,which is booted to 3Vcc-1Vt, thus driving the gate of output transistor134.

[0034] While the circuit of FIG. 2 works well, it is complex andconsequently draws more current than is often desirable. The presentinvention simplifies the FIG. 2 circuitry. FIG. 4 illustrates anexemplary embodiment of the present invention. Using the top portion ofthe circuit 5000, for illustrative purposes, the charge pump system 1000is modified with the addition of new diode 2004 and elimination of thepre-charge capacitor 1640 and the pre-charge circuitry associated withit. By use of diode 2004, the second boot circuit 1060 receives apre-charge voltage at node HØ which is 2Vcc-1Vt. The 2Vcc voltage isreceived from node GØ and is dropped by a single Vt when passing throughdiode 2004. The voltage 2Vcc-1Vt, is used to pre-charge capacitor 1480.Thus, when the clock signal at the input to capacitor 1480 goes high,the voltage at node HØ is now 3Vcc-1Vt, which is sufficient to drive thegate of transistor 134. New diode 2004 can also be placed in aconfiguration where it is back to back with diode 1920 as illustrated inFIG. 7.

[0035] Diode 2004 provides a voltage to node HØ of 2Vcc-1Vt which isgreater than the initial voltage at node GØ by passing the final(booted) GØ voltage to node HØ. Thus, capacitor 1480 is pre-charged tothe final GØ voltage (2Vcc-1Vt) resulting in a final (booted) output of3Vcc-1Vt. Since 3Vcc-1Vt, the final voltage at node HO, is greater thanthe 2Vcc output of the first boot circuit 1040, the source voltage 2Vccat transistor 134 will be driven to Vccp output terminal as 2Vcc.Therefore, the use of single diode 2004 obviates the need for thecomplex pre-charge circuitry of FIG. 2 to pre-charge capacitor 1480.Diode 1920 is still used to route excess charge from HØ to GØ and onthrough 134 to Vccp. This configuration of back to back diodes 1920 and2004 provides very efficient control of nodes GØ and HØ.

[0036] This functionality can be verified by comparing the results ofthe circuit of FIG. 4 graphically depicted in FIG. 5 with that of FIG.3. A close study of the rising edges of GØ (pre-charges capacitor 1380)and HØ (pre-charges capacitor 1480) in synchronization with the clockand clock delayed reveal this fact. Similar to FIG. 3, FIG. 5 shows thatGØ pre-charges capacitor 1380 to Vcc which is booted to 2Vcc.Furthermore, HØ pre-charges capacitor 1480 to 2Vcc-1Vt and which isbooted to 3Vcc-1Vt, thus driving the gate of output transistor 134. Inshort, capacitors 1640 and 1660; transistors 1560, 1580, 1680 and 1700;and diodes 1600 and 1620 may all be eliminated from the FIG. 2 circuitin accordance with the invention. Single diode 2004 maintains nodes GØand HØ at or near values of the prior charge pump system 1000.Therefore, the addition of a single diode drastically increases thehardware efficiency and decreases complexity of the charge pump system1000, while lowering overall current drain.

[0037] The charge pump system 1000 may be fabricated of discretecomponents or as an integrated circuit. If fabricated as an integratedcircuit, it may be fabricated along with the semiconductor circuit towhich it supplies voltage on a substrate of a single die and containedin a single integrated package unit. The voltage pump system 1000 mayalso be fabricated by itself on a substrate of a die and then packagedfor connection with and use with other circuit devices.

[0038]FIG. 6 illustrates a processor-based system 102, including centralprocessing unit (CPU) 112, memory devices 108, 110, input/output (I/O)devices 104, 106, floppy disk drive 114 and CD ROM drive 116. All of theabove components communicate with each other over bus 118. The centralprocessing unit (CPU) 112, and one or more of the memory devices 108,110 may use one or more charge pump systems 1000 for their respectiveoperating voltages.

[0039] It is to be understood that the above description is intended tobe illustrative and not restrictive. Many variations to theabove-described system and method will be readily apparent to thosehaving ordinary skill in the art. For example, the above system andmethod may be employed in multi-phase charge pumps or simply in a singlestage charge pump.

[0040] Accordingly, the present invention is not to be considered aslimited by the specifics of the particular structures which have beendescribed and illustrated, but is only limited by the scope of theappended claims.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A charge pump system for providing a pumpedoutput voltage, said system comprising: a clock generator generating atleast one clock signal; and at least one pump stage, said pump stagecomprising: a first boot circuit for booting a first voltage to a secondvoltage higher than said first voltage using said at least one clocksignal; a second boot circuit for booting a third voltage to a fourthvoltage higher than said third voltage using said at least one clocksignal; a first unidirectional current device disposed between an outputnode of said first boot circuit and an output node of said second bootcircuit, said first unidirectional current device providing a firstpre-charge voltage to said second boot circuit from said first bootcircuit; and an output transistor for delivering a voltage from saidoutput node of said first boot circuit to an output terminal in responseto a signal applied from said output node of said second boot circuit tothe gate of said output transistor.
 2. The system of claim 1, whereinsaid first boot circuit comprises: a capacitor for storing a secondpre-charge voltage when said at least one clock signal is low; and asecond unidirectional current device passing said second pre-chargevoltage to said capacitor.
 3. The system of claim 1 further comprising adelay circuit for producing at least one delayed clock signal, from saidat least one clock signal, as input to said second boot circuit.
 4. Thesystem of claim 3, wherein said second boot circuit comprises acapacitor for storing said first pre-charge voltage received from saidoutput node of said first boot circuit when said at least one delayedclock signal is low.
 5. The system of claim 2 further comprising a delaycircuit for producing at least one delayed clock signal, from said atleast one clock signal, as input to said second boot circuit.
 6. Thesystem of claim 5, wherein said second boot circuit comprises acapacitor for storing said first pre-charge voltage received from saidoutput node of said first boot circuit when said at least one delayedclock signal is low.
 7. The system of claim 3, wherein said at least onedelayed clock signal has a rising edge, which occurs after the risingedge of said at least one clock signal and a falling edge which occursbefore a falling edge of said at least one clock signal.
 8. The systemof claim 3, wherein said delay circuit comprises a single edge delaycircuit.
 9. The system of claim 1, wherein said first unidirectionalcurrent device is part of a circuit formed by back to backunidirectional current devices disposed between said first boot circuitand said second boot circuit.
 10. The systems of claim 1, furthercomprising at least two of said pump stages having their outputterminals connected to a common output terminal, said two pump stagesbeing operated 180° out of phase with respect to each other by saidclock signal.
 11. A processor system comprising: a processor; and amemory device coupled to said processor, at least one of said memorydevice and said processor containing a charge pump system, said chargepump system comprising: a clock generator for generating at least oneclock signal; a first boot circuit for booting a first voltage to asecond voltage higher than said first voltage using said at least oneclock signal; a second boot circuit for booting a third voltage to afourth voltage higher than said third voltage using said at least oneclock signal; a first unidirectional current device disposed between anoutput node of said first boot circuit and an output node of a secondboot circuit, said first unidirectional current device providing a firstpre-charge voltage to said second boot circuit from said first bootcircuit; and an output transistor for delivering a voltage from saidoutput node of said first boot circuit to an output terminal in responseto a signal applied from said output node of said second boot circuit tothe gate of said output transistor.
 12. The processor system of claim11, wherein said first boot circuit comprises: a capacitor for storing asecond pre-charge voltage when said at least one clock signal is low;and a second unidirectional current device passing said secondpre-charge voltage to said capacitor.
 13. The processor system of claim11 further comprising a delay circuit for producing at least one delayedclock signal, from said at least one clock signal, as input to saidsecond boot circuit.
 14. The processor system of claim 13, wherein saidsecond boot circuit comprises a capacitor for storing said firstpre-charge voltage received from said output node of said first bootcircuit when said at least one delayed clock signal is low.
 15. Theprocessor system of claim 12 further comprising a delay circuit forproducing at least one delayed clock signal, from said at least oneclock signal, as input to said second boot circuit.
 16. The processorsystem of claim 15, wherein said second boot circuit comprises acapacitor for storing said first pre-charge voltage received from saidoutput node of said first boot circuit when said at least one delayedclock signal is low.
 17. The system of claim 13, wherein said at leastone delayed clock signal has a rising edge which occurs after the risingedge of said at least one clock signal and a falling edge which occursbefore a falling edge of said at least one clock signal.
 18. Theprocessor system of claim 13, wherein said delay circuit comprises asingle edge delay circuit.
 19. The processor system of claim 11, whereinsaid first unidirectional current device is part of a circuit formed byback to back unidirectional current devices disposed between said firstboot circuit and said second boot circuit.
 20. The processor system ofclaim 11, wherein said memory device contains said charge pump.
 21. Theprocessor system of claim 11, wherein said processor contains saidcharge pump.
 22. The processor system of claim 11, further comprising atleast two of said pump stages having their output terminals connected toa common output terminal, said two pump stages being operated 180° outof phase with respect to each other by said clock signal.
 23. Anintegrated circuit comprising: a die having a charge pump systemfabricated thereon, said charge pump comprising: a clock generator forgenerating at least one clock signal; and at least one charge pump stagecomprising: a first boot circuit for booting a first voltage to a secondvoltage higher than said first voltage using said at least one clocksignal; a second boot circuit for booting a third voltage to a fourthvoltage higher than said third voltage using said at least one clocksignal; a first unidirectional current device disposed between an outputnode of said first boot circuit and an output node of a second bootcircuit, said first unidirectional current device providing a firstpre-charge voltage to said second boot circuit from said first bootcircuit; and an output transistor for delivering a voltage from saidoutput node of said first boot circuit to an output terminal in responseto a signal applied from said output node of said second boot circuit tothe gate of said output transistor.
 24. The integrated circuit of claim23, wherein said first boot circuit comprises: a capacitor for storing asecond pre-charge voltage when said at least one clock signal is low;and a second unidirectional current device passing said secondpre-charge voltage to said capacitor.
 25. The integrated circuit ofclaim 23 further comprising a delay circuit for producing at least onedelayed clock signal, from said at least one clock signal, as input tosaid second boot circuit.
 26. The integrated circuit of claim 25,wherein said second boot circuit comprises a capacitor for storing saidfirst pre-charge voltage received from said output node of said firstboot circuit when said at least one delayed clock signal is low.
 27. Theintegrated circuit of claim 24, further comprising a delay circuit forproducing at least one delayed clock signal, from said at least oneclock signal, as input to said second boot circuit.
 28. The integratedcircuit of claim 27, wherein said second boot circuit comprises acapacitor for storing said first pre-charge voltage received from saidoutput node of said first boot circuit when said at least one delayedclock signal is low.
 29. The integrated circuit of claim 25, whereinsaid at least one delayed clock signal has a rising edge, which occursafter the rising edge of said at least one clock signal and a fallingedge which occurs before a falling edge of said at least one clocksignal.
 30. The integrated circuit of claim 25, wherein said delaycircuit comprises a single edge delay circuit.
 31. The integratedcircuit of claim 23, further comprising at least two of said pump stageshaving their output terminals connected to a common output terminal,said two pump stages being operated 180° out of phase with respect toeach other by said clock signal.
 32. The integrated circuit of claim 23wherein said first unidirectional current device is part of a circuitformed by back to back unidirectional current devices disposed betweensaid first boot circuit and said second boot circuit.
 33. A method ofproviding a charge pump voltage, said method comprising: performing atleast one voltage boosting process, each of said voltage boostingprocess comprising: booting a first voltage to a second voltage higherthan said first voltage in response to a clock signal with a first bootcircuit; booting a third voltage to a fourth voltage higher than saidthird voltage in response to said clock signal with a second bootcircuit; passing an output of said first boot circuit to an output ofsaid second boot circuit through a unidirectional current device topre-charge said second boot circuit; and passing said fourth voltage toan output conductor.
 34. The method of claim 33, further comprisingsupplying said first voltage as a pre-charge voltage to said first bootcircuit through a unidirectional current device.
 35. The method of claim33, further comprising supplying said clock signal to said first bootcircuit and supplying said clock signal to said second boot circuit. 36.The method of claim 35, further comprising performing two of saidboosting processes out of phase with respect to said clock signal andpassing the fourth voltages from each process to a common outputconductor.